Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

Voltage source Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications due to their advantages like modularity better power quality. However, the number of used is significant. In this paper, an improved asymmetrical multilevel inverter topology proposed producing 17-levels output utilizing two dc sources. The circuit developed reduce isolated dc-sources without reducing levels. utilizes six two-quadrant switches, three four-quadrant switches four capacitors. capacitors self-balancing do not require extra attention, i.e. control system simple MLI. Detailed analysis under linear non-linear loading conditions carried out. Comparison with other similar topologies shows that superior in device count, quality, Total Standing (TSV), cost factor. performance validated different load through MATLAB/Simulink environment prototype laboratory. Furthermore, thermal done, losses calculated via PLECS software. offers a total harmonic distortion (THD) 4.79% voltage, all lower order harmonics being less than 5% complying IEEE standards.